In recent years, with miniaturization of semiconductor processes, two kinds of voltages, i.e., an external voltage and an internal voltage, are employed in semiconductor devices, and the internal voltage is set lower than the external voltage. Therefore, there is a necessity for a circuit for converting the logical voltage level of a signal between a circuit driven by the external voltage and a circuit driven by the internal voltage.
Hereinafter, a description will be given of a prior art relating to a circuit for converting a logical voltage corresponding to a low power supply voltage to a logical voltage corresponding to a high power supply voltage (hereinafter referred to as “voltage level conversion circuit”).
As an example of a conventional circuit of this kind, Japanese Published Patent Application No. Hei. 7-321638 (pages 10-11 and 15-16, FIGS. 1-3 and 12-13) discloses a voltage level conversion circuit which is driven by a high power supply voltage.
FIG. 13 is a diagram for explaining the voltage level conversion circuit disclosed in this gazette.
This voltage level conversion circuit 101 includes a first N channel MOS transistor Qn101 which is connected between a first input node Iin and an internal node N101, a first P channel MOS transistor Qp101 which is connected between a high power supply voltage VPP and the internal node N101, and a power supply side second P channel MOS transistor Qp102 and a ground side second N channel MOS transistor Qn102 which are connected in series between the high power supply voltage VPP and a ground voltage VSS.
A first input signal I1 having a logical voltage corresponding to a low power supply voltage VCC is applied to the first input node Iin, and a second input signal S1 having a logical voltage higher than that of the first input signal I1, which is generated on the basis of the first input signal I1, is applied to a second input node Sin. Further, a gate of the first N channel MOS transistor Qn101 is connected to the second input node Sin, and a gate of the first P channel MOS transistor Pn101 is connected to an output node Nout which is a connection point of the second P channel MOS transistor Qp102 and the second N channel MOS transistor Qn102. A gate of the second P channel MOS transistor Qp102 is connected to the internal node N101, and a gate of the second N channel MOS transistor Qn102 is connected to the first input node Iin. A latch circuit for latching the input signal I1 applied to the first input node Iin to output an inversion signal O1 thereof from an output node Nout is constituted by the first and second P channel MOS transistors Qp101 and Qp102.
Next, the operation will be described.
When the first and second input signals I1 and S1 are applied to the first and second input nodes Iin and Sin of the voltage level conversion circuit 101, respectively, the internal node N101 of the voltage level conversion circuit 101 comes to have a voltage level according to the logical level of the first input signal I1.
To be specific, when the logical level of the first input signal I1 is L level, the internal node N101 of the voltage level conversion circuit 101 comes to have L level. At this time, in the voltage level conversion circuit 101, the N channel MOS transistor Qn102 is turned off and the P channel MOS transistor Qp102 is turned on, and an H-level output signal O1 is output from the output node NOUT. Further, at this time, the P channel MOS transistor Qp101 is completely turned off.
In this state, when the logical level of the first input signal I1 transits from L level to H level, the N channel MOS transistor Qn102 is completely turned on. At this time, since the voltage level of the second input signal S1 applied to the gate of the N channel MOS transistor Qn101 is boosted to a voltage level that is higher than the H level voltage VCC of the first input signal I1, the voltage at the node N101 of the voltage level conversion circuit 101 becomes not a voltage that is lower than the power supply voltage (VCC) by the threshold voltage Vth of the transistor (VCC-Vth) but the power supply voltage (VCC), and the P channel MOS transistor Qp102 is approximately turned off.
When the output signal O1 becomes L level, the P channel MOS transistor Qp101 is completely turned on, and the voltage at the node N101 becomes the second power supply voltage VPP, whereby the P channel MOS transistor Qp102 is completely turned off.
In the conventional voltage level conversion circuit 101 as described above, since the N channel MOS transistors are high-breakdown-voltage transistors each having a breakdown voltage corresponding to the high power supply voltage VPP, the threshold values thereof are usually high. Therefore, when the logical voltage of the input signal is lowered, the on-state of the N channel MOS transistor Qn102 becomes imperfect, and it takes time to fix the voltage level of the output signal at L level.
As a countermeasure against the problem that occurs when making the voltage level conversion circuit perform low-voltage operation, the above-mentioned gazette proposes as follows. That is, in the voltage level conversion circuit 101 shown in FIG. 13 wherein the gate voltage of the N channel MOS transistor Qn101 is the power supply voltage VCC, a P channel MOS transistor with a gate being connected to the input node Iin is inserted between the power supply voltage VPP and the P channel MOS transistor Qp102 and, when the input signal changes from H level to L level, the current that flows from the power supply voltage VPP into the output terminal Nout is promptly cutoff.
In this circuit construction, when the input signal changes from H level to L level, the voltage level of the output signal O1 can be quickly fixed to L level. However, it is impossible to solve the essential problem in the low voltage operation of the voltage level conversion circuit, that is, it is still difficult to operate the VPP power supply system N channel MOS transistor having the high power supply voltage VPP as a breakdown voltage, at a voltage lower than the threshold voltage.
As described above, since the conventional voltage level conversion circuit shown in FIG. 13 controls the high-breakdown-voltage transistor having, as a power supply voltage, the external voltage that is a high voltage, with a signal corresponding to the internal voltage that is a low voltage, it is difficult to operate the high-breakdown-voltage transistor when the threshold value of the high-breakdown-voltage transistor is high and the internal voltage is lower than the threshold value. Therefore, such voltage level conversion circuit becomes a disincentive to low power consumption and miniaturization of transistors due to low voltage operation in semiconductor devices.